1. Field of the Invention
This invention relates to integrated circuits and, more particularly, to synchronizer circuits.
2. Description of the Related Art
In an electronic circuit such as a flip-flop, for example, metastability can occur when a signal that is in transition is sampled. In other words, if a signal at the input of a flip-flop is not stable when the clock signal edge is received, then the setup and hold time of the flip-flop has been violated. When this occurs, the output state may be uncertain before finally settling to a stable state. However, neither the output state nor the settling time of the flip-flop can be guaranteed to be correct. This metastability may occur in circuits that use one clock signal to send a signal and a different clock signal to receive the signal (e.g., signals that cross clock domains). To avoid or at least reduce the probability of metastability occurring, circuit designers frequently use circuits referred to as synchronizers. A common synchronizer may include two or more series connected flip-flops which are clocked by the same clock signal. The second or third flip-flop in the synchronizer provides a valid signal that is synchronized to the receiver clock domain.
Although synchronizers are commonly used, they may have drawbacks. One such drawback in using multiple flip-flop synchronizers is signal latency. There can be several full clock cycles of delay in receiving stable data. In some timing critical circuits, this delay may be unacceptable.